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general description the MAX5080/max5081 are 250khz pwm step-down dc-dc converters with an on-chip, 0.3 ? high-side switch. the input voltage range is 4.5v to 40v for the MAX5080 and 7.5v to 40v for the max5081. the output is adjustable from 1.23v to 32v and can deliver up to 1a of load current. both devices utilize a voltage-mode control scheme for good noise immunity in the high-voltage switching envi- ronment and offer external compensation allowing for maximum flexibility with a wide selection of inductor val- ues and capacitor types. the switching frequency is internally fixed at 250khz and can be synchronized to an external clock signal through the sync input. light load efficiency is improved by automatically switching to a pulse-skip mode. all devices include programmable undervoltage lock- out and soft-start. protection features include cycle-by- cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. both devices are available in a space-saving, high-power (2.7w), 16-pin tqfn package and are rated for operation over the -40? to +125? temperature range. applications firewire power supplies automotive distributed power industrial features ? 4.5v to 40v (MAX5080) or 7.5v to 40v (max5081) input voltage range ? 1a output current ? v out range from 1.23v to 32v ? internal high-side switch ? fixed 250khz internal oscillator ? automatic switchover to pulse-skip mode at light loads ? external frequency synchronization ? thermal shutdown and short-circuit protection ? operates over the -40? to +125? temperature range ? space-saving (5mm x 5mm) high-power 16-pin tqfn package MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters ________________________________________________________________ maxim integrated products 1 19-3656; rev 1; 2/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin- package pkg code MAX5080 ate -40? to +125? 16 tqfn-ep* t1655-2 max5081 ate -40? to +125? 16 tqfn-ep* t1655-2 MAX5080 v in 4.5v to 40v on/off c1 r1 r2 c2 pgnd reg lx fb in sync sgnd pgnd ss comp dvreg c- c f v out pgnd c bst c ss d1 d2 l1 c8 c5 r6 r5 c+ bst c7 c6 r3 r4 typical operating circuits firewire is a registered trademark of apple computer, inc. typical operating circuits continued at end of data sheet. * ep = exposed pad. pin configurations appear at end of data sheet.
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, on/ off to sgnd..............................................-0.3v to +45v lx to sgnd .................................................-0.3v to (v in + 0.3v) bst to sgnd ................................................-0.3v to (v in + 12v) bst to lx................................................................-0.3v to +12v pgnd to sgnd .....................................................-0.3v to +0.3v reg, dvreg, sync to sgnd ...............................-0.3v to +12v fb, comp, ss to sgnd ...........................-0.3v to (v reg + 0.3v) c+ to pgnd (MAX5080 only)................(v dvreg - 0.3v) to +12v c- to pgnd (MAX5080 only) ................-0.3v to (v dvreg + 0.3v) continuous current through internal power mosfet (pins 11/12 connected together and pins 13/14 connected together) t j = +125?.........................................................................3a t j = +150?.........................................................................2a continuous power dissipation * (t a = +70?) 16-pin tqfn (derate 33.3mw/? above +70?) ...2666.7mw 16-pin tqfn ( ja )........................................................30?/w 16-pin tqfn ( jc ).......................................................1.7?/w operating temperature range .........................-40? to +125? maximum junction temperature .....................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v in = v on/ off = 12v, v reg = v dvreg , v sync = pgnd = sgnd, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = + 25?.) (note 1) parameter symbol conditions min typ max units MAX5080 4.5 40 input voltage range v in max5081 7.5 40 v v in rising, MAX5080 3.9 4.2 undervoltage lockout threshold uvlo v in rising, max5081 6.8 7.3 v MAX5080 0.4 undervoltage lockout hysteresis uvlo hyst max5081 0.7 v v fb = 0v, MAX5080 10.5 switching supply current (pwm operation) i sw v fb = 0v, max5081 9.5 ma v in = 12v, v out = 3.3v, i out = 1a 84 efficiency v in = 4.5v, v out = 3.3v, i out = 1a (MAX5080) 88 % MAX5080 1.4 2.5 no-load supply current (pfm operation) max5081 1.3 2.3 ma shutdown current i shdn v on/ off = 0v, v in = 40v 200 300 ? on/ off control input voltage threshold v on/ off v on/ off rising 1.20 1.23 1.25 v input voltage hysteresis 0.12 v input bias current v on/ off = 0 to 40v -250 +250 na error amplifier/soft-start soft-start current i ss 81524a reference voltage (soft-start) v ss 1.215 1.228 1.240 v fb regulation voltage v fb i comp = -500? to +500? 1.215 1.228 1.240 v fb input range 0 1.5 v fb input current -250 +250 na comp voltage range i comp = -500? to +500? 0.25 4.50 v open-loop gain 80 db unity-gain bandwidth 1.8 mhz * as per jedec 51 standard
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = v on/ off = 12v, v reg = v dvreg , v sync = pgnd = sgnd, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = + 25?.) (note 1) parameter symbol conditions min typ max units fb offset voltage i comp = -500? to +500? -5 +5 mv oscillator frequency f sw v sync = 0v 225 250 275 khz v sync = 0v, v in = 4.5v, MAX5080 87 v sync = 0v, v in = 7.5v, max5081 87 maximum duty cycle d max v sync = 0v, v in 40v 87 % sync high-level voltage 2.2 v sync low-level voltage 0.8 v sync frequency range f sync 150 350 khz pwm modulator gain f sync = 150khz to 350khz 10 v/v ramp level shift (valley) 0.3 v power switch switch on-resistance v bst - v lx = 6v 0.3 0.6 ? switch gate charge v bst - v lx = 6v 6 nc switch leakage current v in = 40v, v lx = v bst = 0v 10 ? bst leakage current v bst = v lx = v in = 40v 10 ? charge pump c- output voltage low MAX5080 only, sinking 10ma 0.1 v c- output voltage high MAX5080 only, relative to dvreg, sourcing 10ma 0.1 v dvreg to c+ on-resistance MAX5080 only, sourcing 10ma 10 ? lx to pgnd on-resistance sinking 10ma 12 ? current-limit comparator pulse-skip threshold i pfm 100 200 300 ma cycle-by-cycle current limit i ilim 1.4 2 2.6 a number of consecutive ilim events to hiccup 7 hiccup timeout 512 clock periods internal voltage regulator MAX5080 4.75 5 5.25 output voltage v reg max5081 7.6 8 8.4 v v in = 5.5v to 40v, MAX5080 1 line regulation v in = 9.0v to 40v, max5081 1 mv/v load regulation i reg = 0 to 20ma 0.25 v v in = 4.5v, i reg = 20ma, MAX5080 0.5 dropout voltage v in = 7.5v, i reg = 20ma, max5081 0.5 v
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = v on/ off = 12v, v reg = v dvreg , v sync = pgnd = sgnd, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = + 25?.) (note 1) parameter symbol conditions min typ max units thermal shutdown thermal shutdown temperature temperature rising +160 c thermal shutdown hysteresis 20 c note 1: 100% production tested at t a = +25? and t a = t j = +125?. limits at -40? are guaranteed by design. typical operating characteristics (v in = 12v, see figure 5 (MAX5080) and figure 6 (max5081), t a = +25?, unless otherwise noted.) undervoltage lockout hysteresis vs. temperature (MAX5080) MAX5080 toc01 temperature ( c) undervoltage lockout hysteresis (v) 110 85 35 60 10 -15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -40 135 undervoltage lockout hysteresis vs. temperature (max5081) MAX5080 toc02 temperature ( c) undervoltage lockout hysteresis (v) 110 85 35 60 10 -15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -40 135 on/off threshold hysteresis vs. temperature MAX5080 toc03 temperature ( c ) on/off threshold hysteresis (v) 110 85 60 35 10 -15 0.05 0.10 0.15 0.20 0 -40 135 shutdown supply current vs. input voltage (MAX5080) MAX5080 toc04 input voltage (v) shutdown supply current ( a) 35 30 20 25 10 15 5 25 50 75 100 125 150 175 200 225 250 0 040 t a = +135 c t a = +25 c t a = +85 c t a = -40 c v on/off = 0v shutdown supply current vs. input voltage (max5081) MAX5080 toc05 input voltage (v) shutdown supply current ( a) 35 30 20 25 10 15 5 25 50 75 100 125 150 175 200 225 250 275 300 0 040 t a = +135 c t a = +25 c t a = +85 c t a = -40 c v on/off = 0v no-load supply current vs. input voltage (MAX5080) MAX5080 toc06 input voltage (v) supply current (ma) 35 30 5 10 15 20 25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 040 t a = +135 c t a = +25 c t a = +85 c t a = -40 c
operating frequency vs. temperature MAX5080 toc07 temperature ( c) operating frequency (khz) 110 85 35 60 10 -15 242 244 246 248 250 252 254 256 258 260 240 -40 135 v in = 4.5v v in = 40v maximum duty cycle vs. input voltage (MAX5080) MAX5080 toc08 input voltage (v) maximum duty cycle (%) 35 30 20 25 10 15 5 82 84 86 88 90 92 94 96 98 100 80 040 maximum duty cycle vs. input voltage (max5081) MAX5080 toc09 input voltage (v) maximum duty cycle (%) 35 30 20 25 10 15 5 82 84 86 88 90 92 94 96 98 100 80 040 MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters _______________________________________________________________________________________ 5 typical operating characteristics (continued) (v in = 12v, see figure 5 (MAX5080) and figure 6 (max5081), t a = +25?, unless otherwise noted.) open-loop gain/phase vs. frequency MAX5080 toc10 frequency (khz) gain (db) phase (degrees) 1000 100 10 1 0.1 0.01 0.001 0 20 40 60 80 100 -20 75 100 125 150 175 50 0 10,000 gain phase output current limit vs. input voltage MAX5080 toc11 input voltage (v) output current limit (a) 35 30 20 25 10 15 5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 1.5 040 MAX5080 t a = +135 c t a = +25 c t a = +85 c t a = -40 c turn-on/off waveform MAX5080 toc12 i load = 1a v out 2v/div v on/off 2v/div 2ms/div turn-on/off waveform MAX5080 toc13 v on/off 2v/div v out 2v/div 2ms/div i load = 100ma
typical operating characteristics (continued) (v in = 12v, see figure 5 (MAX5080) and figure 6 (max5081), t a = +25?, unless otherwise noted.) MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters 6 _______________________________________________________________________________________ efficiency vs. load current MAX5080 toc16 load current (a) efficiency (%) 0.1 0.01 20 30 40 50 60 70 80 90 100 0 0.001 1 v out = 5v v in = 12v v in = 7.5v v in = 40v v in = 24v max5081 load-transient response MAX5080 toc17 v in = 12v, i out = 0.25a to 1a MAX5080 v out ac-coupled 200mv/div i load 500ma/div 200 s/div 0 output voltage vs. temperature MAX5080 toc14 temperature ( c) output voltage (v) 110 85 35 60 10 -15 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 3.20 -40 135 MAX5080 i load = 0a i load = 1a efficiency vs. load current MAX5080 toc15 load current (a) efficiency (%) 0.1 0.01 20 30 40 50 60 70 80 90 100 0 0.001 1 v out = 3.3v v in = 4.5v v in = 7.5v v in = 40v MAX5080 v in = 24v v in = 12v
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v in = 12v, see figure 5 (MAX5080) and figure 6 (max5081), t a = +25?, unless otherwise noted.) lx voltage and inductor current MAX5080 toc19 v lx 5v/div inductor current 200ma/div 2 s/div i load = 40ma lx voltage and inductor current MAX5080 toc20 v lx 5v/div inductor current 100ma/div 2 s/div i load = 140ma 0 lx voltage and inductor current MAX5080 toc21 v lx 5v/div inductor current 500ma/div 2 s/div i load = 1a 0 load-transient response MAX5080 toc18 v in = 4.5v, i out = 0.25a to 1a MAX5080 v out ac-coupled 500mv/div i load 500ma/div 200 s/div 0
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters 8 _______________________________________________________________________________________ detailed description the MAX5080/max5081 are voltage-mode buck con- verters with internal 0.3 ? power mosfet switches. the MAX5080 has a wide input voltage range of 4.5v to 40v. the max5081? input voltage range is 7.5v to 40v. the internal low r ds_on switch allows for up to 1a of output current. the 250khz fixed switching frequency, external compensation, and voltage feed-forward sim- plify loop compensation design and allow for a variety of l and c filter components. both devices offer an automatic switchover to pulse-skipping (pfm) mode, providing low quiescent current and high efficiency at light loads. under no load, a pfm mode operation reduces the current consumption to only 1.4ma. in shutdown, the supply current falls to 200?. additional features include an externally programmable undervolt- age lockout through the on/ off pin, a programmable soft-start, cycle-by-cycle current limit, hiccup mode output short-circuit protection, and thermal shutdown. pin MAX5080 max5081 name function 11 comp error amplifier output. connect comp to the compensation feedback network. 22fb feedback regulation point. connect to the center tap of a resistive divider from converter output to sgnd to set the output voltage. the fb voltage regulates to the voltage present at ss (1.23v). 33 on/ off on/ off and external uvlo control. the on/ off rising threshold is set to approximately 1.23v. connect to the center tap of a resistive divider from in to sgnd to set the uvlo (rising) threshold. pull on/ off to sgnd to shut down the device. on/ off can be used for power- supply sequencing. connect to in for always-on operation. 44ss soft-start and reference output. connect a capacitor from ss to sgnd to set the soft-start time. see the applications information section to calculate the value of the css capacitor. 55 sync oscillator synchronization input. sync can be driven by an external 150khz to 350khz clock to synchronize the MAX5080/max5081? switching frequency. connect sync to sgnd when not used. 66 dvreg gate drive supply for high-side mosfet driver. connect externally to reg for MAX5080. connect to reg and the anode of the boost diode for max5081. 7 c+ charge-pump flying capacitor positive connection 8 c- charge-pump flying capacitor negative connection 7, 8 n.c. no connection. not internally connected. can be left floating or connected to sgnd. 99 pgnd power ground connection. connect the input filter capacitor? negative terminal, the anode of the freewheeling diode, and the output filter capacitor? return to pgnd. connect externally to sgnd at a single point near the input capacitor? return terminal. 10 10 bst high-side gate driver supply. connect bst to the cathode of the boost diode and to the positive terminal of the boost capacitor. 11, 12 11, 12 lx source connection of internal high-side switch. connect the inductor and rectifier diode? cathode to lx. 13, 14 13, 14 in supply input connection. connect to an external voltage source from 4.5v to 40v (MAX5080) or a 7.5v to 40v (max5081). 15 15 reg internal regulator output. 5v output for the MAX5080 and 8v output for the max5081. bypass to sgnd with at least a 1? ceramic capacitor. 16 16 sgnd signal ground connection. solder the exposed pad to a large sgnd plane. connect sgnd and pgnd together at one point near the input bypass capacitor return terminal. ep ep ep exposed pad. connect exposed pad to sgnd. pin description
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters _______________________________________________________________________________________ 9 internal linear regulator (reg) reg is the output terminal of a 5v (MAX5080), or 8v (max5081) ldo which is powered from in and pro- vides power to the ic. connect reg externally to dvreg to provide power for the high-side mosfet gate driver. bypass reg to sgnd with a ceramic capacitor of at least 1?. place the capacitor physically close to the MAX5080/max5081 to provide good bypassing. during normal operation, reg is intended for powering up only the internal circuitry and should not be used to supply power to external loads. internal uvlo/external uvlo the MAX5080/max5081 provides two undervoltage lockouts (uvlos). an internal uvlo looks at the input voltage (v in ) and is fixed at 4.1v (MAX5080) or 7.1v (max5081). an external uvlo is sensed and pro- grammed at the on/ off pin. the external uvlo over- rides the internal uvlo when the external uvlo is higher than the internal uvlo. during startup, before any operation begins, the input voltage and the voltage at on/ off must exceed their respective uvlos. the external uvlo has a rising threshold of 1.23v with 0.12v of hysteresis. program the external uvlo by connecting a resistive divider from in to on/ off to sgnd. connect on/ off to in directly to disable the external uvlo. driving on/ off to ground places the MAX5080/ max5081 in shutdown. when in shutdown the internal power mosfet turns off, all internal circuitry shuts down and the quiescent supply current reduces to 200?. connect an rc network from on/ off to sgnd to set a turn-on delay that can be used to sequence the output voltages of multiple devices. MAX5080 1.23v 1.23v on/off dvreg pclk ldo en in reg ss fb thermal shdn ref in 0.3v clk 1.23v regok en v ref v ref i ss >1.23v on <1.11v off comp sync e/a ssa cpwm ramp logic en osc charge-pump management pclk bst in sgnd lx pgnd sclk high-side current sense ref_pfm pfm ref_ilim ilim overl clk ilim overload management dvreg c+ dvreg c- level shift figure 1. MAX5080 simplified block diagram
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters 10 ______________________________________________________________________________________ soft-start and reference (ss) ss is the 1.23v reference bypass connection for the MAX5080/max5081 and also controls the soft-start period. at startup, after v in is applied and the internal and external uvlo thresholds are reached, the device enters soft-start. during soft-start, 15? is sourced into the capacitor (c ss ) connected from ss to sgnd caus- ing the reference voltage to ramp up slowly. when v ss reaches 1.23v the output becomes fully active. set the soft-start time (t ss ) using following equation: where t ss is in seconds and c ss is in farads. internal charge pump (MAX5080) the MAX5080 features an internal charge pump to enhance the turn-on of the internal mosfet, allowing for operation with input voltages down to 4.5v. connect a flying capacitor (c f ) between c+ and c-, a boost diode from c+ to bst, as well as a bootstrap capacitor (c bst ) between bst and lx to provide the gate drive voltage for the high-side n-channel dmos switch. during the on-time, the flying capacitor is charged to v dvreg . during the off-time, the positive terminal of the flying capacitor (c+) is pumped to two times v dvreg and charge is dumped onto c bst to provide twice the regulator voltage across the high-side dmos driver. use a ceramic capacitor of at least 0.1? for c bst and c f located as close to the device as possible. t vc a ss ss = 123 15 . max5081 1.23v 1.23v on/off ldo en in reg ss fb thermal shdn ref in 0.3v clk ilim 1.23v regok en v ref v ref i ss >1.23v on <1.11v off comp sync e/a ssa cpwm ramp logic en osc bootstrap control pclk bst in sgnd lx dvreg pgnd sclk high-side current sense ref_pfm pfm ref_ilim ilim overl clk ilim overload management figure 2. max5081 simplified block diagram
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters ______________________________________________________________________________________ 11 for applications that do not require a 4.5v minimum input, use the max5081. in this device the charge pump is omitted and the input voltage range is from 7.5v to 40v. in this situation the boost diode and the boost capacitor are still required (see the max5081 typical operating circuit ). gate drive supply (dvreg) dvreg is the supply input for the internal high-side mosfet driver. the power for dvreg is derived from the output of the internal regulator (reg). connect dvreg to reg externally. we recommend the use of an rc filter (1 ? and 0.47?) from reg to dvreg to fil- ter the noise generated by the switching of the charge pump. in the MAX5080, the high-side drive supply is generated using the internal charge pump along with the bootstrap diode and capacitor. in the max5081, the high-side mosfet driver supply is generated using only the bootstrap diode and capacitor. error amplifier the output of the internal error amplifier (comp) is avail- able for frequency compensation (see the compensation design section). the inverting input is fb, the noninvert- ing input ss, and the output comp. the error amplifier has an 80db open-loop gain and a 1.8mhz gbw prod- uct. see the typical operating character-istics for the gain and phase vs. frequency graph. oscillator/synchronization input (sync) with sync tied to sgnd, the MAX5080/max5081 use their internal oscillator and switch at a fixed frequency of 250khz. for external synchronization, drive sync with an external clock from 150khz to 350khz. when driven with an external clock, the device synchronizes to the rising edge of sync. pwm comparator/voltage feedforward an internal 250khz ramp generator is compared against the output of the error amplifier to generate the pwm signal. the maximum amplitude of the ramp (v ramp ) automatically adjusts to compensate for input voltage and oscillator frequency changes. this causes the v in /v ramp to be a constant 10v/v across the input voltage range of 4.5v to 40v (MAX5080) or 7.5v to 40v (max5081) and the sync frequency range of 150khz to 350khz. output short-circuit protection (hiccup mode) the MAX5080/max5081 protects against an output short circuit by utilizing hiccup-mode protection. in hiccup mode, a series of sequential cycle-by-cycle current-limit events will cause the part to shut down and restart with a soft-start sequence. this allows the device to operate with a continuous output short circuit. during normal operation, the current is monitored at the drain of the internal power mosfet. when the current limit is exceeded, the internal power mosfet turns off until the next on-cycle and a counter increments. if the counter counts seven consecutive current-limit events, the device discharges the soft-start capacitor and shuts down for 512 clock periods before restarting with a soft-start sequence. each time the power mosfet turns on and the device does not exceed the current limit, the counter is reset. thermal-overload protection the MAX5080/max5081 feature an integrated thermal- overload protection. thermal-overload protection limits the total power dissipation in the device and protects it in the event of an extended thermal fault condition. when the die temperature exceeds +160?, an internal thermal sensor shuts down the part, turning off the power mosfet and allowing the ic to cool. after the temperature falls by 20?, the part will restart with a soft-start sequence. applications information setting the undervoltage lockout when the voltage at on/ off rises above 1.23v, the MAX5080/max5081 turns on. connect a resistive divider from in to on/ off to sgnd to set the uvlo threshold (see figure 5). first select the on/ off to the sgnd resistor (r2) then calculate the resistor from in to on/ off (r1) using the following equation: where v in is the input voltage at which the converter turns on, v on/ off = 1.23v and r2 is chosen to be less than 600k ? . if the external uvlo divider is not used, connect on/ off to in directly. in this case, an internal under- voltage lockout feature monitors the supply voltage at in and allows operation to start when in rises above 4.1v (MAX5080) and 7.1v (max5081). setting the output voltage connect a resistive divider from out to fb to sgnd to set the output voltage. first calculate the resistor from out to fb using the guidelines in the compensation design section. once r3 is known, calculate r4 using the following equation: rr v v 12 1 = ? ? ? ? ? ? ? ? ? in on/ off
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters 12 ______________________________________________________________________________________ where v fb = 1.23v. inductor selection three key inductor parameters must be specified for operation with the MAX5080/max5081: inductance value (l), peak inductor current (i peak ), and inductor saturation current (i sat ). the minimum required induc- tance is a function of operating frequency, input-to-out- put voltage differential, and the peak-to-peak inductor current ( ? i p-p ). higher ? i p-p allows for a lower inductor value while a lower ? i p-p requires a higher inductor value. a lower inductor value minimizes size and cost and improves large-signal and transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. on the other hand, higher inductance increases efficiency by reducing the ripple current. resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels especial- ly when the inductance is increased without also allow- ing for larger inductor dimensions. a good compromise is to choose ? i p-p equal to 40% of the full load current. calculate the inductor using the following equation: v in and v out are typical values so that efficiency is opti- mum for typical conditions. the switching frequency (f sw ) is fixed at 250khz or can vary between 150khz and 350khz when synchronized to an external clock (see the oscillator/synchronization input (sync) section). the peak-to-peak inductor current, which reflects the peak-to- peak output ripple, is worst at the maximum input voltage. see the output capacitor selection section to verify that the worst-case output ripple is acceptable. the inductor saturating current (i sat ) is also important to avoid run- away current during continuous output short circuit. select an inductor with an i sat specification higher than the maximum peak current limit of 2.6a. input capacitor selection the discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to keep the input voltage ripple within design requirements. the input voltage ripple is comprised of ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the input capacitor). the total voltage ripple is the sum of ? v q and ? v esr . calculate the input capacitance and esr required for a specified ripple using the following equations: where i out_max is the maximum output current, d is the duty cycle, and f sw is the switching frequency. the MAX5080/max5081 includes internal and external uvlo hysteresis and soft-start to avoid possible unin- tentional chattering during turn-on. however, use a bulk capacitor if the input source impedance is high. use enough input capacitance at lower input voltages to avoid possible undershoot below the undervoltage lockout threshold during transient loading. output capacitor selection the allowable output voltage ripple and the maximum deviation of the output voltage during load steps deter- mine the output capacitance and its esr. the output ripple is mainly composed of ? v q (caused by the capacitor discharge) and ? v esr (caused by the volt- age drop across the equivalent series resistance of the output capacitor). the equations for calculating the peak-to-peak output voltage ripple are: normally, a good approximation of the output voltage ripple is ? v ripple ? v esr + ? v q . if using ceramic capacitors, assume the contribution to the output volt- age ripple from esr and the capacitor discharge to be ? ? ?? v i 1 vi q pp out sw esr p - p = = 6c f esr () ? i vv v vl d v v p - p in out out in sw out in = = ? f and esr v i idd f = + ? ? ? ? ? ? = ? ? ? ? esr out_max p - p in out_max qsw i c 1 v 2 () () l f = ? vvv vi out in out in sw p - p ? r r v v 4 3 1 = ? ? ? ? ? ? ? out fb
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters ______________________________________________________________________________________ 13 equal to 20% and 80%, respectively. ? i p-p is the peak-to- peak inductor current (see the input capacitors selection section) and f sw is the converter? switching frequency. the allowable deviation of the output voltage during fast load transients also determines the output capaci- tance, its esr, and its equivalent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the converter (see the compensation design section). the resistive drop across the output capacitors esr, the drop across the capacitors esl ( ? v esl) , and the capacitor discharge causes a voltage droop during the load- step. use a combination of low-esr tantalum/aluminum electrolyte and ceramic capacitors for better transient load and voltage ripple performance. nonleaded capacitors and capacitors in parallel help reduce the esl. keep the maximum output voltage deviation below the tolerable limits of the electronics being pow- ered. use the following equations to calculate the required esr, esl, and capacitance value during a load step: where i step is the load step, t step is the rise time of the load step, and t response is the response time of the controller. compensation design the MAX5080/max5081 use a voltage-mode control scheme that regulates the output voltage by comparing the error amplifier output (comp) with an internal ramp to produce the required duty cycle. the output lowpass lc filter creates a double pole at the resonant frequen- cy, which has a gain drop of -40db/decade. the error amplifier must compensate for this gain drop and phase shift to achieve a stable closed-loop system. the basic regulator loop consists of a power modulator, an output feedback divider, and a voltage error amplifi- er. the power modulator has a dc gain set by v in /v ramp , with a double pole and a single zero set by the output inductance (l), the output capacitance (c out ) (c5 in the typical application circuit ) and its equivalent series resistance (esr). the power modula- tor incorporates a voltage feed-forward feature, which automatically adjusts for variations in the input voltage resulting in a dc gain of 10. the following equations define the power modulator: the switching frequency is internally set at 250khz or can vary from 150khz to 350khz when driven with an external sync signal. the crossover frequency (f c ), which is the frequency when the closed-loop gain is equal to unity, should be set at 15khz or below therefore: f c 15khz the error amplifier must provide a gain and phase bump to compensate for the rapid gain and phase loss from the lc double pole. this is accomplished by utiliz- ing a type 3 compensator that introduces two zeroes and 3 poles into the control loop. the error amplifier has a low-frequency pole (f p1 ) near the origin. the two zeros are at: and the higher frequency poles are at: compensation when f c < f zesr figure 3 shows the error amplifier feedback as well as its gain response for circuits that use low-esr output capacitors (ceramic). in this case f zesr occurs after f c . f z1 is set to 0.8 x f lc(mod) and f z2 is set to f lc to com- pensate for the gain and phase loss due to the double pole. choose the inductor (l) and output capacitor (c out ) as described in the inductor and output capacitor selection section. f rc and f r cc cc pp 23 1 266 1 25 78 78 = = + ? ? ? ? ? ? f 1 f 1 z1 z2 = = + 257 2 636 rc and rr c () () g v v f lc f c esr mod dc in ramp lc out zesr out == = = 10 1 2 1 2 e v c v e v esr step out step response q esl step step sr i it sl t i = = = ? ? ?
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters 14 ______________________________________________________________________________________ pick a value for the feedback resistor r5 in figure 3 (values between 1k ? and 10k ? are adequate). c7 is then calculated as: f c occurs between f z2 and f p2 . the error-amplifier gain (g ea ) at f c is due primarily to c6 and r5. therefore, g ea(fc) = 2 x f c x c6 x r5 and the modulator gain at f c is: since g ea(fc) x g mod(fc) = 1, c6 is calculated by: f p2 is set at 1/2 the switching frequency (f sw ). r6 is then calculated by: since r3 >> r6, r3 + r6 can be approximated as r3. r3 is then calculated as: f p3 is set at 5xf c . therefore c8 is calculated as: compensation when f c > f zesr for larger esr capacitors such as tantalum and alu- minum electrolytic ones, f zesr can occur before f c . if f zesr < f c , then f c occurs between f p2 and f p3 . f z1 and f z2 remain the same as before however, f p2 is now set equal to f zesr . the output capacitor? esr zero fre- quency is higher than f lc but lower than the closed- loop crossover frequency. the equations that define the error amplifier? poles and zeroes (f z1 , f z2 , f p1 , f p2 , and f p3 ) are the same as before. however, f p2 is now lower than the closed-loop crossover frequency. figure 4 shows the error amplifier feedback as well as its gain response for circuits that use higher-esr output capac- itors (tantalum or aluminum electrolytic). pick a value for the feedback resistor r5 in figure 4 (val- ues between 1k ? and 10k ? are adequate). c7 is then calculated as: the error amplifier gain between f p2 and f p3 is approxi- mately equal to r5/r6 (given that r6 << r3). r6 can then be calculated as: c6 is then calculated as: c c esr r 6 6 = out r rf f lc c 6 510 2 2 c 1 f lc 7 208 5 = .r () c c crf 8 7 275 1 = ? p3 r fc 3 1 26 lc . r cf 6 1 2605 = sw c flc rg c 6 2 5 = out mod(dc) () g g lc f c mod(fc) mod(dc) out = 2 22 c 1 f lc 7 208 5 = .r gain (db) v out ref r3 comp r6 r5 c6 r4 frequency closed-loop gain ea gain f z1 f z2 f c f p2 f p3 c8 ea c7 figure 3. error amplifier compensation circuit (closed-loop and error-amplifier gain plot) for ceramic capacitors
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters ______________________________________________________________________________________ 15 since r3 >> r6, r3 + r6 can be approximated as r3. r3 is then calculated as: f p3 is set at 5xf c . therefore, c8 is calculated as: power dissipation the MAX5080/max5081 is available in a thermally enhanced package and can dissipate up to 2.7w at t a = +70?. when the die temperature reaches +160?, the part shuts down and is allowed to cool. after the parts cool by 20?, the device restarts with a soft-start. the power dissipated in the device is the sum of the power dissipated from supply current (p q ), transition losses due to switching the internal power mosfet (p sw ), and the power dissipated due to the rms cur- rent through the internal power mosfet (p mosfet ). the total power dissipated in the package must be lim- ited such that the junction temperature does not exceed its absolute maximum rating of +150? at maxi- mum ambient temperature. calculate the power lost in the MAX5080/max5081 using the following equations: the power loss through the switch: p mosfet = i rms_mosfet 2 x r on r on is the on-resistance of the internal power mosfet (see electrical characteristics ). the power loss due to switching the internal mosfet: where t r and t f are the rise and fall times of the internal power mosfet measured at lx. the power loss due to the switching supply current (i sw ): p q = v in x i sw the total power dissipated in the device will be: p total = p mosfet + p sw + p q chip information transistor count: 4300 process: bicmos/dmos () p f sw sw = vi tt in out r f 4 () _ pi xr iiiii d ii i ii i mosfet rms mosfet on rms mosfet pk pk dc dc pk out pp dc out pp = =++ ? ? ? ? ? ? =+ =? ? ? 2 22 3 2 2 _ ? ? () c c crf 8 7 275 1 = ? p3 r fc 3 1 26 lc gain (db) v out ref r3 comp r6 r5 c6 r4 frequency closed-loop gain ea gain f z1 f z2 f c f p2 f p3 c8 ea c7 figure 4. error amplifier compensation circuit (closed-loop and error amplifier gain plot) for higher esr output capacitors
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters 16 ______________________________________________________________________________________ figure 6. max5081 typical application circuit typical application circuits MAX5080 v in 4.5v to 40v on/off c1 10 f r1 1.4m ? r2 549k ? c2 0.1 f c10 0.1 f pgnd reg lx fb in sync sgnd pgnd ss comp dvreg c- c3 0.1 f v out pgnd c4 0.1 f c9 0.047 f d1 d2 l1 47 h c8 820pf c5 47 f r6 187 ? r5 3.01k ? c+ bst c7 22nf c6 6.8nf r3 6.81k ? r4 4.02k ? figure 5. MAX5080 typical application circuit max5081 v in 7.5v to 40v on/off c1 10 f r1 1.4m ? r2 301k ? c2 0.1 f c10 0.1 f pgnd reg lx fb in sync sgnd pgnd ss comp dvreg v out pgnd c4 0.1 f c9 0.047 f d1 d2 l1 47 h c8 820pf c5 47 f r6 187 ? r5 3.01k ? bst c7 22nf c6 6.8nf r3 6.81k ? r4 4.02k ?
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters ______________________________________________________________________________________ 17 pin configurations top view 12 13 14 15 16 8 7 6 5 11 10 9 1234 lx lx bst pgnd c- c+ dvreg sync in sgnd comp fb on/off ss in reg MAX5080 tqfn 12 13 14 15 16 8 7 6 5 11 10 9 1234 lx lx bst pgnd n.c. n.c. dvreg sync in sgnd comp fb on/off ss in reg max5081 tqfn typical operating circuits (continued) max5081 v in 7.5v to 40v on/off c1 r1 r2 c2 pgnd reg lx fb in sync sgnd pgnd ss comp dvreg v out pgnd c bst c ss d1 d2 l1 c8 c5 r6 r5 bst c7 c6 r3 r4
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters 18 ______________________________________________________________________________________ qfn thin.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
MAX5080/max5081 1a, 40v, maxpower step-down dc-dc converters maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) revision history pages changed at rev 1: 1, 8, 18, 19

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